In portable battery operated products such as a selective call receiver, it is desirable to have the lowest possible current drain in order to maximize battery life. Conventional selective call receivers may use conventional phase lock loop(s) to synthesize frequencies needed for digital logic or radio frequency circuits. These components operate in a fashion such that when switched from a first frequency to a second frequency, an output frequency is achieved relative to a reference frequency. The problem here is that during switching, the output frequency variations and ultimate tracking are limited by the loop response as determined by a loop filter. By design, conventional phase lock loops typically require a prescaler (commonly referred to as a divide-by-N counter) that scales the output frequency such that it may be coupled to a phase/frequency detector and the loop filter to control a voltage controlled oscillator. The voltage controlled oscillator in turn produces the output frequency responsive to the phase/frequency difference detected by the phase/frequency detector and further in response to the time and frequency domain characteristics of the loop filter. The components of the phase lock system, especially the loop filter, are typically designed for optimal performance at a selected divide-by-N count and corresponding output frequency. This constraint produces compromised performance at frequencies other than that produced by the selected divide-by-N count since the loop gain varies with respect to the division ratio selected. Moreover, since the filter topology is typically low pass, constraints on frequency variations due to overshooting or undershooting the desired frequency are primarily determined by the filter characteristics. Many artisans have, with no success, attempted to solve the problems associated with the above loop gain versus operating frequency compromise. Furthermore, conventional phase lock loop systems operating in the above described manner may, during the frequency switching mode, drive the voltage controlled oscillator's output frequency so far from the desired output frequency that the loop will lock on a spurious response or not at all.
Hence, conventional phase lock loop synthesizers do not minimize total power consumption because of their relatively uncontrolled variations during frequency locking and tracking. Attempts to improve power consumption and response characteristics have yielded topologies that are extremely complicated, requiring additional circuitry and more than eliminating any power saving and performance advantages gained.
Thus, what is needed is a phase lock loop frequency synthesizer topology that effectively conserves power while offering improved frequency switching, locking, and tracking characteristics.